Suyash is a cryptography researcher at Ingonyama. He is primarily interested is in making zero-knowledge proofs faster (and better). He holds a masters and bachelors in Electrical engineering from IIT Bombay with specialisation in applied cryptography.
In this chapter, we explore sum-check protocols from the point of view of parallelizable computation in devices such as GPUs. We explore algorithmic modifications to the sum-check protocol, for products of Multi-Linear Extensions (MLE) to improve parallel compute and address memory bottlenecks.